
February 2012, OCPIP

This directory contains a set of testbenches for the TL0-to-TL1 and TL1-to-TL0 adapters.  

The testbenches illustrate how to use the adapters.

Each testbench contains:
- two implementations of an OCP initiator, one in TL1 and the other in TL0.
- two implementations of an OCP target, one in TL1 and the other in TL0.
- 6 assemblies, testing identical behaviour for TL0-only, TL1-only, TL0-to-TL1, TL1-to-TL0, TL1-to-TL0-to-TL1 and TL0-to-TL1-to-TL0.

The testbenches are self-checking and also dump traces which can be checked for differences.

To run the entire set of testbenches and test correctness, type "make" in this directory after installing the OCP Modelling Kit and the adapters package.

Known issues with the testbenches:
- The TL1 targets are in some of the testbenches insensitive to the burst_length extension and assume aligned TLM2 addresses where this should not be assumed.
- All the targets, TL0 and TL1, fail to respect OCP ordering rules for RD/WR hazards
- Except in the "reset" testbench, the TL1/TL0 targets' implementation of OCP reset is not tested and does not resynchronise the incoming reset signal as required by the OCP specification
- In the "reset" testbench some manual tuning has been done to ensure identical behaviour in all assemblies.  This may not be possible in general.
- In the "semaph" testbench, the write transaction following a RDEX does not have the same address as the RDEX as required by the OCP Specification

Testbench list:
- simple
  POD types for TL0 signals, no bursts, no byte enables
- sctypes
  same function using SystemC data types for TL0 signals
- mrmdburst
- srmdburst
  includes DataLast / RespLast
- outoforder
  SRMD bursts with multiple outstanding and out-of-order responses
- threads
  SRMD bursts with non-blocking flow control and out-of-order datahs+responses
- srmdseq
  complex bursts: BLCK, WRAP, STRM, XOR
  byte enable
  WNP & W, no resp for W
- mrmdseq
  complex bursts: non-precise INCR
  complex bursts: UNKN, DFLT1/2
  complex bursts: non-aligned (including TLM2 non-aligned to bus width)
  W without response
- semaph
  RDL, WRC
  RDEX
  WNP & W mixed with responses for both
- reset
  (also uses SystemC data types)
  MReset and SReset
  req-info, resp-info and m/sdata-info, using user-supplied conversion functions
  MFlag / SFlag, using user-supplied conversion functions
  SInterrupt
  MError and SError
  Address space
  Conn-ID

The OCP configuration space is covered by these testbenches but not completely.  Features implemented in the adapters but not tested include:
- req-last
- req-row-last
- tag-in-order
- mbyteen / mdatabyteen differences and all combinations of byte-enable-length
- MRMD address sequences for WRAP, XOR, BLCK, STRM
- SRMD DFLT1/2
- atomic length
- many combinations of TLM transaction alignment
- many combinations of exotic burst address or streaming or row width
- simulation starting in OCP reset
- reset during RDEX

The following features are not implemented in the adapters:
- broadcast
- BLCK bursts with stride not OCP-aligned
- changes to sample timing during simulation
- disconnect

