This directory contains an example for OCP profile:

X Bus Profiles

These interfaces support cacheable and non-cacheable instruction and data
traffic between a CPU and the memories and register interfaces of other
targets. These profiles might be used with a CPU core that internally 
used the AMBA AXI protocols, and were externally bridged to OCP.

X Write Bus Profile (master_w)

This profile is designed to create OCP master wrappers to native interfaces
of CPU type initiators with single-request/multiple-data, write-only
transactions.

X Read Bus Profile (master_r)

This profile helps you create OCP master wrappers for native interfaces of
CPU type initiators with single-request multiple-data read-only transactions.

1. Edit the SYSTEMC and TARGET_ARCH variables in the Makefile

2. run gmake

3. run ocp_tl1 ocpParam1 ocpParam2
