# Example of parameter configuration, file format is compatible with OCP IP standard.  "#" is used for comments
# Here we configure the DRAM according to Krishnan's paper and the 256Mb X8 DDR1 DRAM on Page 3 JEDEC DDR RAM specification, clocked at 200MHz

# IO clock period, in SC_NS
clockPeriod i:5

# DRAM data rate, use 0 for "SDR", 1 for "DDR1", 2 for "DDR2", 3 for "DDR3"
dataRate i:1

# DRAM refresh period, in SC_NS
refreshPeriod i:7600

# DRAM refresh duration, in SC_NS
refreshDuration i:120

# bit width of the address bus
addressBusWidth i:25

# bit width of bank address
bankAddressWidth i:2

# bit width of row address
rowAddressWidth i:13

# bit width of column address
columnAddressWidth i:10

# DRAM IO width
dataWidth i:4

# DRAM Minimum burst length
burstLength i:4

# Delay caused by hop rows, in SC_NS
tHopRow i:55

# Delay between a Activate and a RD/WR command, in SC_NS
tRCD i:15

# Delay between Read and the first response
tCAS i:10

# Delay between Write and the first data gets registered
tDQSS i:10

# Delay between a Read and the last write data gets registered
tWTR i:10
